ARMv7: introduce Cortex-A17

Signed-off-by: Etienne Carriere <[email protected]>

diff --git a/include/lib/cpus/aarch32/cortex_a17.h b/include/lib/cpus/aarch32/cortex_a17.h
new file mode 100644 (file)
index 0000000..d2ca91c
--- /dev/null
+++ b/include/lib/cpus/aarch32/cortex_a17.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __CORTEX_A17_H__
+#define __CORTEX_A17_H__
+
+/*******************************************************************************
+ * Cortex-A17 midr with version/revision set to 0
+ ******************************************************************************/
+#define CORTEX_A17_MIDR                        0x410FC0E0
+
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define CORTEX_A17_ACTLR_SMP_BIT       (1 << 6)
+
+#endif /* __CORTEX_A17_H__ */

diff --git a/lib/cpus/aarch32/cortex_a17.S b/lib/cpus/aarch32/cortex_a17.S
new file mode 100644 (file)
index 0000000..316d4f0
--- /dev/null
+++ b/lib/cpus/aarch32/cortex_a17.S
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <assert_macros.S>
+#include <cortex_a17.h>
+#include <cpu_macros.S>
+
+       .macro assert_cache_enabled
+#if ENABLE_ASSERTIONS
+               ldcopr  r0, SCTLR
+               tst     r0, #SCTLR_C_BIT
+               ASM_ASSERT(eq)
+#endif
+       .endm
+
+func cortex_a17_disable_smp
+       ldcopr  r0, ACTLR
+       bic     r0, #CORTEX_A17_ACTLR_SMP_BIT
+       stcopr  r0, ACTLR
+       isb
+       dsb     sy
+       bx      lr
+endfunc cortex_a17_disable_smp
+
+func cortex_a17_enable_smp
+       ldcopr  r0, ACTLR
+       orr     r0, #CORTEX_A17_ACTLR_SMP_BIT
+       stcopr  r0, ACTLR
+       isb
+       bx      lr
+endfunc cortex_a17_enable_smp
+
+func cortex_a17_reset_func
+       b       cortex_a17_enable_smp
+endfunc cortex_a17_reset_func
+
+func cortex_a17_core_pwr_dwn
+       push    {r12, lr}
+
+       assert_cache_enabled
+
+       /* Flush L1 cache */
+       mov     r0, #DC_OP_CISW
+       bl      dcsw_op_level1
+
+       /* Exit cluster coherency */
+       pop     {r12, lr}
+       b       cortex_a17_disable_smp
+endfunc cortex_a17_core_pwr_dwn
+
+func cortex_a17_cluster_pwr_dwn
+       push    {r12, lr}
+
+       assert_cache_enabled
+
+       /* Flush L1 caches */
+       mov     r0, #DC_OP_CISW
+       bl      dcsw_op_level1
+
+       bl      plat_disable_acp
+
+       /* Exit cluster coherency */
+       pop     {r12, lr}
+       b       cortex_a17_disable_smp
+endfunc cortex_a17_cluster_pwr_dwn
+
+declare_cpu_ops cortex_a17, CORTEX_A17_MIDR, \
+       cortex_a17_reset_func, \
+       cortex_a17_core_pwr_dwn, \
+       cortex_a17_cluster_pwr_dwn